1. Field of the Invention
This invention relates to a computer system and, more particularly, to a memory subsystem within the computer system employing extended data out (EDO) dynamic random access memory (DRAM). Even more specifically, this invention relates to the prevention of bus contention between EDO DRAM banks during burst accesses having a non-deterministic length.
2. Description of the Relevant Art
Modern computer systems often employ extended data out (EDO) dynamic random access memory (DRAM) in order to obtain faster memory cycle times. The basic operation of EDO DRAM devices and the addressing of such devices by row address strobe (RAS) signals and column address strobe (CAS) signals and the design of controllers for such devices, is generally understood in the art of memory control/access and, for sake of brevity, need not be repeated.
EDO DRAM continues to drive the addressed data on its data lines after CAS is unasserted. This extended output drive allows the device(s) accessing the memory to latch the data during the CAS precharge time of the next memory cycle, resulting in a shorter cycle time. Multiple banks of memory are desirable for improved capacity and performance. However, if multiple banks of EDO DRAM are employed, a data bus contention problem may arise when memory accesses switch from one bank to another during burst accesses. The contention problem arises because the previously selected EDO DRAM bank continues to drive the data bus. When the newly selected memory bank begins to drive data for the addressed location, both banks will be contending for, and driving, the bus.
Therefore, it is necessary to turn off the output drivers of the previously selected bank before the newly selected (current) bank begins to drive the data bus. Several solutions have been utilized to turn off the previously selected bank's output drivers to avoid contention.
One such solution is not to use EDO-type DRAM and instead employ a type of memory that does not continue to drive the bus, such as regular fast page mode DRAM. This solution has the disadvantage of losing the performance benefits of EDO DRAM.
Another solution is to use the output enable (OE) pin for the EDO DRAM to turn off the output drivers when switching to a new bank. However, the OE pin is normally not required for use in normal operation, and thus is usually not driven by the memory controller device. The OE pin on each EDO DRAM is usually hardwired to an enabled state. Therefore, to employ this solution, extra pins would need to be added to the memory controller device to drive the OE pins of the EDO DRAM for each separate memory bank. However, extra pins may not be available to the memory controller. At the very least, it is expensive to support the extra pins needed to drive the OE signals. Therefore, it is desirable to have a solution that turns off the EDO DRAM output drivers by using signals already in use, thus avoiding the addition of more pins to the memory controller.
Another solution is to only access the system memory with burst cycles that always end on a bank boundary. When the burst cycle ends on a bank boundary, both RAS and CAS are unasserted to that memory bank. The EDO DRAM output drivers turn off when both RAS and CAS are unasserted. However, it may be advantageous to employ burst cycles of a non-deterministic length. If the burst length is non-deterministic, then it cannot be guaranteed that the burst will end on a bank boundary.
An example of a system employing non-deterministic burst lengths is a system in which a central processing unit (CPU) and a graphics controller both access memory in a shared memory architecture. The graphics controller may have an internal first-in first-out (FIFO) storage to maintain the screen image without interruption when the CPU is accessing system memory. When the graphics controller obtains access to system memory, it will perform a burst access cycle to fill its FIFO. The length of the burst required to fill the FIFO will vary depending on system operation. Limiting the FIFO to bursts of determined length may result in the graphics controller being "starved" for memory. Thus, it is desirable to employ a non-deterministic burst length to optimize graphics controller accesses. It is easily understood that other types of devices and architectures could benefit from non-deterministic burst lengths.
Therefore, it is desirable to have a memory system that employs EDO DRAM in multiple banks, but avoids data contention when switching between banks. For improved performance, it is also desirable to leave the memory page open (not deassert RAS) when switching banks so that page hits may continue. It is further desirable to avoid data contention without requiring additional control signals to the memory controller device. Furthermore, it is desirable for such a system to support burst accesses of a non-deterministic length to memory.